Embodiments of the present invention relate to semiconductor devices, and more particularly to determining an anticipated lifetime for such devices.
Measuring the lifetime of semiconductor devices (i.e., its time to failure) is a concern with current and future technologies, since transistors and other structures become smaller and degrade faster. Existing methods to predict the lifetime of such devices are static methods that assume fixed conditions for the entire device lifetime in terms of temperature, voltage and frequency. However, the dynamic behavior can be very different from the fixed conditions assumed. Additionally, each resource within an integrated circuit (IC) works under different conditions, leading to different lifetimes for different resources.
Lifetime of devices shortens from generation to generation. Furthermore, lifetime depends on actual operating parameters, such as different operating voltages and temperatures, and different technologies' scaling trends. This decreasing lifetime comes from a number of sources of degradation: electromigration, stress migration, time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) and thermal cycling. The failure rate due to these factors is assumed to be distributed evenly across the five sources. This failure rate is commonly referred to as failures in time (FIT), which is the expected number of failures in 109 hours. Using a FIT value one can obtain the mean time to failure (MTTF), a measure commonly used in the industry, as 1/FIT. For any technology, MTTF is obtained assuming steady state operation at fixed conditions (e.g., temperature, voltage, frequency and utilization).
However, temperature, voltage, frequency and utilization can all vary along the circuit lifetime, and thus steady state mechanisms fail to accurately predict the lifetime of devices. Accordingly a need exists for improved lifetime measurements.